1. Field of the Invention
The present invention relates to adder circuits. More specifically, the present invention relates to adders implemented with gallium arsenide technology.
While the present invention is described herein with reference to an illustrative embodiment for a particular application, it is understood that the invention is not limited thereto. Those of ordinary skill in the art and access to the teachings provided herein will recognize additional modifications, applications and embodiments within the scope thereof.
2. Description of the Related Art
High speed adders are at the heart of many digital systems. For example, high speed adders are used with holding registers to provide accumulators used in direct digital synthesizers. Direct digital synthesizers provide fine resolution in frequency step size for frequency synthesizers. Since the maximum frequency out of a direct digital synthesizer must be less than half its clock frequency the bandwidth and resolution of frequency synthesizers is limited by the adder/clock. Thus, there is a general need in the art to increase the speed of such adders.
Previous emitter coupled logic (ECL) and transistor transistor logic (TTL) fast adder designs utilized adders and carry look ahead logic which made extensive use of large fan-in merged logic gates. (See Fairchild's F100180 six-bit fast adder, for example.) It is generally known in the art that for some applications, gallium arsenide GaAs technology offers the potential for higher speed and lower power consumption relative to ECL and TTL technologies.
Unfortunately, merged logic gates with a high fanin become impractical in very high speed FET GaAs logic. This is due to the fact that the parasitic capacitive loading effects of the multiple inputs become more predominant, vis-a-vis gate speed as the speed and fan-in increases. That is, at high speed with high fan-in, these effects constitute a larger fraction of the gate propagation delays.
The operating speed of each adder is also limited by finite gate delays. It follows that the number of gates required to generate the sum and carry outputs impacts directly on the operating speed of the adder. In most adders, as the size of the adder increases, the number of cascaded stages increases accordingly. Thus, in cascaded adders, the number of gate delays required to generate the carry in each adder is of particular importance.
There is therefore a need in the art for a cascadable fast adder configuration which may be implemented in gallium arsenide technology.